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cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v flex18? 3.3 v 128 k / 256 k / 512 k 18 synchronous dual-port ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06059 rev. *w revised october 13, 2011 flex18? 3.3 v 128 k / 256 k / 512 k 18 synchronous dual-port ram features true dual-ported memory cells that allow simultaneous access of the same memory location synchronous pipelined operation family of 2-mbit, 4-mbit, and 9-mbit devices pipelined output mode allows fast operation 0.18 micron cmos for optimum speed and power high speed clock to data access 3.3 v low power ? active as low as 225 ma (typ) ? standby as low as 55 ma (typ) mailbox function for message passing global master reset separate byte enables on both ports commercial and industrial temperature ranges ieee 1149.1 compatible jtag boundary scan 144-ball fbga (13 mm 13 mm) (1.0 mm pitch) 120-pin tqfp (14 mm 14 mm 1.4 mm) pb-free packages available counter wrap around control ? internal mask register co ntrols counter wrap around ? counter-interrupt flags to indicate wrap around ? memory block retransmit operation counter readback on address lines mask register readback on address lines dual chip enables on both ports for easy depth expansion functional description the flex18? family includes 2-mbit, 4-mbit, and 9-mbit pipelined, synchronous, true dual port static rams that are high speed, low power 3.3 v cmos. two ports are provided, permitting independent, simultaneous access to any location in memory. the result of writing to the same location by more than one port at the same time is undefined. registers on control, address, and data lines allow for minimal setup and hold time. during a read oper ation, data is registered for decreased cycle time. each port contains a burst counter on the input address register. after externally loading the counter with the initial address, the counter increments the address internally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the sh ortest possible cycle times. a high on ce 0 or low on ce 1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. one cycle with chip enables asserted is required to reactivate the outputs. additional features include: r eadback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap around, counter interrupt (cntint ) flags, readback of mask register value on address lines, retransmit functionality, inte rrupt flags for message passing, jtag for boundary scan, and asynchronous master reset (mrst ). the cy7c0833v device in this family has limited features. see address counter and mask register operations on page 7 for details. product selection guide density 2 mbit (128 k 18) 4 mbit (256 k 18) 9 mbit (512 k 18) part number cy7c0831av cy7c0832av cy7c0832bv [1] cy7c0833v maximum speed (mhz) 133 167 133 100 maximum access time - clock to data (ns) 4.0 4.0 4.4 4.7 typical operating current (ma) 225 225 225 270 package 120-pin tqfp 120-pin tqfp 120-pin tqfp 144-ball fbga note 1. cy7c0832av and cy7c0832bv are functionally identical.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 2 of 31 logic block diagram [2] a 0l ?a 18l clk l ads l cnten l cntrst l true ram array 19 addr. read back cntint l mask register counter/ address register cnt/msk l address decode dual-ported interrupt logic int l reset logic jtag tdo tms tck tdi mrst dq 9l ?dq 17l dq 0l ?dq 8l i/o control 9 9 ce 0l ce 1l r/w l b0 l b1 l oe l a 0r ?a 18r clk r ads cnten cntrst r 19 addr. read back cntint r mask register counter/ address register cnt/msk r address decode interrupt logic int r i/o control 9 9 ce 0r ce 1r r/w r b0 r b1 r oe r mirror reg mirror reg dq 0r ?dq 8r dq 9r ?dq 17r note 2. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 3 of 31 contents pin configurations ........................................................... 4 pin definitions .................................................................. 6 byte select operation ...................................................... 7 master reset ..................................................................... 7 mailbox interrupts ........................................................ 7 address counter and mask register operations ........ 7 counter reset operation ............................................ 8 counter load operation .............................................. 8 counter increment operation ...................................... 8 counter hold operation .............................................. 8 counter interrupt ......................................................... 8 counter readback operation ...................................... 8 retransmit ................................................................... 9 mask reset operation ................................................. 9 mask load operation .................................................. 9 mask readback operation .......................................... 9 counting by two ......................................................... 9 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 11 performing a tap re set ........................................... 11 performing a pause/restart ... ................................... 11 boundary scan hierarchy for 9 -mbit device ............. 11 identification register definitions ................................ 12 scan registers sizes ..................................................... 12 instruction identification codes .................................... 12 maximum ratings ........................................................... 13 operating range ............................................................. 13 electrical characteristics ............................................... 13 capacitance .................................................................... 13 ac test load and waveforms ....................................... 14 switching characteristics .............................................. 14 jtag timing and switching waveforms ..................... 16 switching waveforms .................................................... 17 ordering information ...................................................... 26 512 k 18 (9 m) 3.3 v synchronous cy7c0833v dual-port sram ........... 26 256 k 18 (4 m) 3.3 v synchronous cy7c0832av/cy7c0832bv dual-p ort sram ................ 26 128 k 18 (2 m) 3.3 v synchronous cy7c0831av dual-port sram ........ 26 ordering code definitions ..... .................................... 26 package diagrams .......................................................... 27 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 document history page ................................................. 29 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc solutions ......................................................... 31
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 4 of 31 pin configurations figure 1. 144-ball bga (top view) cy7c0833v 1 2 3 4 5 6 7 8 9 10 11 12 a dq17 l dq16 l dq14 l dq12 l dq10 l dq9 l dq9 r dq10 r dq12 r dq14 r dq16 r dq17 r b a0 l a1 l dq15 l dq13 l dq11 l mrst nc dq11 r dq13 r dq15 r a1 r a0 r c a2 l a3 l ce1 l [3] int l cntint l [4] ads l [5] ads r [5] cntint r [4] int r ce1 r [3] a3 r a2 r d a4 l a5 l ce 0 l [5] nc vdd vdd vdd vdd nc ce 0 r [5] a5 r a4 r e a6 l a7 l b 1 l nc vdd vss vss vdd nc b 1 r a7 r a6 r f a8 l a9 l c l nc vss vss vss vss nc c r a9 r a8 r g a10 l a11 l b 0 l nc vss vss vss vss nc b 0 r a11 r a10 r h a12 l a13 l oe l nc vdd vss vss vdd nc oe r a13 r a12 r j a14 l a15 rw l nc vdd vdd vdd vdd nc rw r a15 r a14 r k a16 l a17 l cnt/msk l [3] tdo cntrst l [3] tck tms cntrst r [3] tdi cnt/msk r [3] a17 r a16 r l a18 l nc dq6 l dq4 l dq2 l cnten l [5] cnten r [5] dq2 r dq4 r dq6 r nc a18 r m dq8 l dq7 l dq5 l dq3 l dq1 l dq0 l dq0 r dq1 r dq3 r dq5 r dq7 r dq8 r notes 3. these balls are not applicable for cy7c 0833v device. they must be tied to vdd. 4. these balls are not applicable for cy7c 0833v device. they must not be connected. 5. these balls are not applicable for cy7c 0833v device. they must be tied to vss.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 5 of 31 figure 2. 120-pin tqfp (top view) cy7c0831av / cy7c0832av / cy7c0832bv pin configurations (continued) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 dq 11l cntint l int l dq 9l dq 10l dq 12l v ss v dd dq 13l dq 14l dq 15l dq 16l dq 17l a 0l a 1l dq 16r a 1r a 0r dq 17r dq 15r dq 14r dq 13r v dd v ss dq 12r dq 11r dq 10r dq 9r int r cntint r 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 b 1r v ss v dd ce 0r oe r b 0r ce 1r a 7r a 6r a 5r a 4r v dd v ss a 3r a 2r a 12r a 13r v dd v ss a 11r a 10r a 9r a 8r cnt/msk r cntrst r cnten r ads r mrst clk r r/w r 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 v ss dq 0l dq 1l dq 2l dq 3l v dd dq 4l dq 5l dq 6l dq 7l dq 8l a 17l a 16l a 15l a 14l a 17r a 14r a 15r a 16r dq 8r dq 7r dq 6r dq 5r dq 4r v dd v ss dq 3r dq 2r dq 1r dq 0r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b 1l v ss v dd ce 0l oe l b 0l a 7l a 6l a 5l a 4l v dd v ss a 3l a 2l a 12l a 13l v dd v ss a 11l a 10l a 9l a 8l cnt/msk l cntrst l cnten l ads l v ss clk l r/w l ce 1l [6] [6] note 6. leave this pin unconnected for cy7c0831av.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 6 of 31 pin definitions left port right port description a 0l ?a 18l [7] a 0r ?a 18r [7] address inputs . ads l [8] ads r [8] address strobe input . used as an address qualifier. this signal should be asserted low for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. ce 0l [8] ce 0r [8] active low chip enable input . ce 1l [9] ce 1r [9] active high chip enable input . clk l clk r clock signal . maximum clock input rate is f max . cnten l [8] cnten r [8] counter enable input . asserting this signal low increments the burst address counter of its respective port on each rising edge of clk. the increment is disabled if ads or cntrst are asserted low. cntrst l [9] cntrst r [9] counter reset input . asserting this signal low resets to zero the unmasked portion of the burst address counter of its respective port. cntrst is not disabled by asserting ads or cnten . cnt/msk l [9] cnt/msk r [9] address counter mask register enable input . asserting this signal low enables access to the mask register. when tied high, the mask regi ster is not accessible and the address counter operations are enabled based on the st atus of the counter control signals. dq 0l ?dq 17l dq 0r ?dq 17r data bus input/output . oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrupt flag output . the mailbox permits communications between ports. the upper two memory locations are us ed for message passing. int l is asserted low when the right port writes to the mailbox location of the left port, an d vice versa. an interrupt to a port is deasserted high when it reads the contents of its mailbox. cntint l [10] cntint r [10] counter interrupt output . this pin is asserted low when the unmasked portion of the counter is incremented to all ?1s.? r/w l r/w r read/write enable input . assert this pin low to write to, or high to read from the dual port memory array. b 0l ?b 1l b 0r ?b 1r byte select inputs . asserting these signals enables read and write operations to the corre- sponding bytes of the memory array. mrst master reset input . mrst is an asynchronous input signal and affects both ports. asserting mrst low performs all of the reset functions as described in the text. a mrst operation is required at power up. tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck. tdi jtag test data input . data on the tdi input is shifted serially into selected registers. tck jtag test clock input . tdo jtag test data output . tdo transitions occur on the falling edge of tck. tdo is normally three-stated except when captured data is shifted out of the jtag tap. v ss ground inputs . v dd power inputs . notes 7. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits. 8. these balls are not applicable for cy7c 0833v device. they must be tied to vss. 9. these balls are not applicable for cy7c 0833v device. they must be tied to vdd. 10. these balls are not applicable for cy7c 0833v device. they must not be connected.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 7 of 31 master reset the flex18 family devices undergo a complete reset by taking its mrst input low. the mrst input can switch asynchronously to the clocks. an mrst initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). mrst also forces the mailbox interrupt (int ) flags and the counter interrupt (cntint ) flags high. mrst must be performed on the flex18 family devices after power up. mailbox interrupts the upper two memory locations may be used for message passing and permit communications between ports. table 1 on page 8 shows the interrupt operation for both ports of cy7c0833v. the highest memory location, 7ffff is the mailbox for the right port and 7f ffe is the mailbox for the left port. table 1 on page 8 shows that to set the int r flag, a write operation by the left port to address 7ffff asserts int r low. at least one byte has to be active for a write to generate an interrupt. a valid read of the 7ffff location by the right port resets int r high. at least one byte must be active for a read to reset the interrupt. when one port writes to the other port?s mailbox, the int of the port that the mailbox belongs to is asserted low. the int is reset when the owner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-through mode (that is, it follows the clock edge of the writing port). also, the flag is reset in a flow-through mode (that is, it follows the clo ck edge of the reading port). each port can read the other po rt?s mailbox without resetting the interrupt. and each port can write to its own mailbox without setting the interrupt. if an application does not require message passing, int pins should be left open. address counter and mask register operations this section [11] describes the features only apply to 2-mbit and 4-mbit devices. it does not apply to 9 mbit device. each port of these devices has a programmable burst address counter. the burst counter contains three regi sters: a counter register, a mask register, and a mirror register. the counter register contains the address used to access the ram array. it is changed only by the counter load, increment, counter reset, and by master reset (mrst ) operations. the mask register value affects the increment and counter reset operations by preventing the corresponding bits of the counter register from changing. it also affects the counter interrupt output (cntint ). the mask register is changed only by the mask load and mask reset operations and by the mrst . the mask register defines the counting range of the counter register. it divides the counter register into two regions: zero or more ?0s? in the most significant bits define the masked region, one or more ?1s? in the least significant bits define the unmasked region. bit 0 may also be ?0,? masking the least significant counter bit and causing the counter to in crement by two instead of one. the mirror register is used to reload the counter register on increment operations (see retransmit on page 9 ). it always contains the value last loaded in to the counter register, and is changed only by the counter load, and by the mrst instructions. table 2 on page 9 summarizes the operation of these registers and the required input control signals. the mrst control signal is asynchronous. all the other control signals in table 2 on page 9 (cnt/msk , cntrst , ads , cnten ) are synchronized to the port?s cl k. all these counter and mask operations are independent of the port?s chip enable inputs (ce0 and ce1). counter enable (cnten ) inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast, interleaved memory applications. a port?s burst counter is loaded when the port?s address strobe (ads ) and cnten signals are low. when the port?s cnten is asserted and the ads is deasserted, the address counter increments on each low to high transition of that port?s clock signal. this reads and writes one word from and to each successive addr ess location until cnten s deasserted. the counter can address the entire memory array, and loops back to the start. co unter reset (cntrst ) is used to reset the unmasked portion of the burst counter to i/0s. a counter-mask register is used to control the counter wrap. byte select operation control pin effect b 0 dq 0?8 byte control b 1 dq 9?17 byte control note 11. this section describes the cy7c0832av/cy7c0832bv and cy7c0831av having 18 and17 address bits.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 8 of 31 counter reset operation all unmasked bits of the counter are reset to ?0.? all masked bits remain unchanged. the mirror register is loaded with the value of the burst counter. a mask reset followed by a counter reset resets the counter and mirror registers to 00000, as does master reset (mrst ). counter load operation the address counter and mirror registers are both loaded with the address value presented at the address lines. counter increment operation when the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addr essing the entire memory array. only the unmasked bits of the co unter register are incremented. the corresponding bit in the mask register must be a ?1? for a counter bit to change. the counte r register is incremented by 1 if the least significant bit is unma sked, and by 2 if it is masked. if all unmasked bits are ?1,? the ne xt increment wraps the counter back to the initially loaded value. if an increment results in all the unmasked bits of the counter being ?1s,? a counter interrupt flag (cntint ) is asserted. the next increment returns the counter register to its initial value, which was stored in the mirror register. the counter address can instead be forced to loop to 00000 by externally connecting cntint to cntrst . [18] an increment that results in one or more of the unmasked bits of the counter being ?0? deasserts the counter interrupt flag. the example in figure 4 on page 11 shows the counter mask register loaded with a mask value of 0003fh unmasking the first 6 bits with bit ?0? as the lsb and bit ?16? as the msb. the maximum value the mask register can be loaded with is 3ffffh. setting the mask register to this value allows the counter to acce ss the entire memory space. the address counter is then loaded with an initial value of 8h. the base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment after the counter is configured for increment operation. the counter address starts at address 8h. the counter increments its internal address value until it r eaches the mask register value of 3fh. the counter wraps around the memory block to location 8h at the next count. cntint is issued when the counter reaches its maximum value counter hold operation the value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. such operation is useful in applicati ons where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. counter interrupt the counter interrupt (cntint ) is asserted low when an increment operation results in the unmasked portion of the counter register being all ?1s.? it is deasserted high when an increment operation results in any other value. it is also de-asserted by counter reset, counter load, mask reset and mask load operations, and by mrst . counter readback operation the internal value of the counter register can be read out on the address lines. readback is pipelined; the address is valid t ca2 after the next rising edge of the port?s clock. if address readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) are three-stated. figure 3 on page 10 shows a block diagram of the operation. table 1. interrupt operation example [12, 13, 14, 15, 16, 17] function left port right port r/w l ce l a 0l ?a 18l int l r/w r ce r a 0r ?a 18r int r set right int r flag l l3ffffxxxxl reset right int r flag xxxxhl3ffffh set left int l flag xxxl l l3fffex reset left int l flag hl3fffehxxxx set right int r flag l l3ffffxxxxl notes 12. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits. 13. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data is out after the following clk edge and is three-stated after the next clk edge. 14. oe is ?don?t care? for mailbox operation. 15. at least one of be0 , be1 must be low. 16. a18x is a nc for cy7c0832av/cy7c0832bv, therefore the interru pt addresses are 3ffff and 3fffe. a18x and a17x are nc for cy7c 0831av, therefore the interrupt addresses are 1ffff and 1fffe. 17. ?x? = ?don?t care,? ?h? = high, ?l? = low. 18. cntint and cntrst specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 9 of 31 retransmit retransmit is a feature that allows the read of a block of memory more than once without the need to reload the initial address. this eliminates the need for external logic to store and route data. it also reduces the comp lexity of the system design and saves board space. an internal mi rror register is used to store the initially loaded address counter value. when the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this mirror register. if the counter is cont inuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the mirror register. thus, the repeated access of the same data is allowed without the need for any external logic. mask reset operation the mask register is reset to all ?1s,? which unmasks every bit of the counter. master reset (mrst ) also resets the mask register to all ?1s?. mask load operation the mask register is loaded wit h the address value presented at the address lines. not all values permit correct increment operations. permitted values are of the form 2 n ? 1 or 2 n ? 2. from the most significant bit to the least significant bit, permitted values have zero or more ?0s,? one or more ?1s,? or one ?0.? thus 3ffff, 003fe, and 00001 are permitted values, but 3f0ff, 003fc, and 00000 are not. mask readback operation the internal value of the mask re gister can be read out on the address lines. readback is pipelined; the address is valid t cm2 after the next rising edge of the port?s clock. if mask readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) is three-stated. figure 3 on page 10 shows a block diagram of the operation. counting by two when the least significant bit of the mask register is ?0,? the counter increments by two. this may be used to connect the 18 devices as a 36-bit single port sram in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. this even-odd address scheme stores one half of the 36-bit data in even memory locations, and the other half in odd memory locations. table 2. address counter and counter-mask register control operation (any port) [19, 20] clk mrst cnt/msk cntrst ads cnten operation description x l x x x x master reset reset address c ounter to all 0s and mask register to all 1s. h h l x x counter reset reset counter unmasked portion to all 0s. h h h l l counter load load counter with external address value presented on address lines. h h h l h counter readback read out counter internal value on address lines. h h h h l counter increment internally increment address counter value. h h h h h counter hold constantly hold the address value for multiple clock cycles. h l l x x mask reset reset mask register to all 1s. h l h l l mask load load mask register with value presented on the address lines. h l h l h mask readback read out mask register value on address lines. h l h h x reserved operation undefined notes 19. ?x? = ?don?t care,? ?h? = high, ?l? = low. 20. counter operation and mask register operation is independent of chip enables.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 10 of 31 figure 3. counter, mask, and mirror logic block diagram [21] from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to counter bit 0 wrap 17 17 17 17 17 1 0 load/increment cnt/msk cnten ads cntrst clk decode logic bidirectional address lines mask register counter/ address register from address lines to readback and address decode 17 17 mrst note 21. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 11 of 31 ieee 1149.1 serial boundary scan (jtag) [24] the flex18 family devices incorporate an ieee 1149.1 serial boundary scan test access port (tap). the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 compliant taps. the tap operates using jedec-standard 3.3 v i/o logic levels. it is composed of three input connections and one output connection required by the test logic defin ed by the standard. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the devices, and may be performed while the device is operating. an mrst must be performed on the devices after power up. performing a pause/restart when a shift-dr pause-dr shift-dr is performed the scan chain outputs the next bit in the chain twice. for example, if the value expected from the chain is 1010101, the device outputs a 11010101. this extra bit causes some testers to report an erroneous failure for the devices in a scan test. therefore the tester should be configured to never enter the pause-dr state. boundary scan hierarchy for 9-mbit device internally, the cy7c0833v have two dies. each die contain all the circuitry required to support boundary scan testing. the circuitry includes the tap, tap controller, instruction register, and data registers. the circ uity and operation of the die boundary scan are described in detail below. the scan chain of each die are connected serially to form the scan chain of the cy7c0833v as shown in figure 5 on page 12 . tms and tck are connected in parallel to each die to drive all tap controllers in unison. in many cases, eac h die is supplied with the same instruction. in other cases, it mi ght be useful to supply different instructions to each die. one example would be testing the device id of one die while bypassing the others. each pin of flex18 family is typi cally connected to multiple dies. for connectivity testing with the extest instruction, it is desirable to check the internal connections between dies and the external connections to the package. this is accomplished by merging the netlist of the devic es with the netlist of the user?s circuit board. to facilitate boundary scan testing of the devices, cypress provides the bsdl file for each die, the internal netlist of the device, and a description of the device scan chain. the user can use these materials to easily integrate the devices into the board?s boundary scan environment. figure 4. programmable counter-mask register operation [22, 23] 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 01 00 xs 1 x 0 x 0 x0 11 xs 1 x 1 x 1 x1 00 xs 1 x 0 x 0 x0 masked address unmasked address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register notes 22. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits. 23. the ?x? in this diagram represents the counter upper bits 24. boundary scan is ieee 1149.1-compatible. see performing a pause/restart on page 11 for deviation from strict 1149.1 compliance
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 12 of 31 figure 5. scan chain for 9 mb device d2 tdo tdi d1 tdo tdi tdi tdo identification regi ster definitions instruction field value description revision number (31:28) 0h reserved for version number. cypress device id (27:12) c090h defines cypress part number for cy7c0832av/cy7c0832bv c091h defines cypress part number for cy7c0831av cypress jedec id (11:1) 034h allows unique identification of the dp family device vendor. id register presence (0) 1 indicates the presence of an id register. scan registers sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [25] instruction iden tification codes instruction code description extest 0000 captures the input/output ring cont ents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places the register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces all device output drivers to a high z state. clamp 0100 controls boundary to 1/0. places byr between tdi and tdo. sample/preload 1000 captures the input/output ri ng contents. places bsr between tdi and tdo. nbsrst 1100 resets the non-boundary scan logic. places byr between tdi and tdo. reserved all other codes other combinations ar e reserved. do not use other than the above. note 25. see details in the device bsdl file.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 13 of 31 maximum ratings exceeding maximum ratings [26] may impair the useful life of the device. these user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied .. .............. ........... ....... ?55 c to +125 c supply voltage to ground potential .............?0.5 v to +4.6 v dc voltage applied to outputs in high z state ...................... ?0.5 v to v dd + 0.5 v dc input voltage ........................... ?0.5 v to v dd + 0.5 v [27] output current into outputs (low) ............................ 20 ma static discharge voltage (jedec jesd22-a114-2000b) .. .............. ................ > 2000v latch up current ................................................... > 200 ma operating range range ambient temperature v dd commercial 0 c to +70 c 3.3 v 165 mv industrial ?40 c to +85 c 3.3 v 165 mv electrical characteristics over the operating range parameter description -167 -133 -100 unit min typ max min typ max min typ max v oh output high voltage (v dd = min, i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v dd = min, i ol = +4.0 ma) ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ih input high voltage 2.0 ? ? 2.0 ? ? 2.0 ? ? v v il input low voltage ? ? 0.8 ? ? 0.8 ? ? 0.8 v i oz output leakage current ?10 ? 10 ?10 ? 10 ?10 ? 10 ? a i ix1 input leakage current except tdi, tms, mrst ?10 ? 10 ?10 ? 10 ?10 ? 10 ? a i ix2 input leakage current tdi, tms, mrst ?0.1 ? 1.0 ?0.1 ? 1.0 ?0.1 ? 1.0 ma i cc operating current for (v dd = max, i out = 0 ma), outputs disabled cy7c0831av cy7c0832av cy7c0832bv ? 225 300 ? 225 300 ? ? ? ma cy7c0833v ? ? ? ? 270 400 ? 200 310 ma i sb1 [28] standby current (both ports ttl level) ce l and ce r ? v ih , f = f max ?90115?90115?90115ma i sb2 [28] standby current (one port ttl level) ce l | ce r ? v ih , f = f max ? 160 210 ? 160 210 ? 160 210 ma i sb3 [28] standby current (both ports cmos level) ce l and ce r ? v dd ? 0.2 v, f = 0 ?5575?5575?5575ma i sb4 [28] standby current (one port cmos level) ce l | ce r ? v ih , f = f max ? 160 210 ? 160 210 ? 160 210 ma i sb5 operating current (v dd = max, i out = 0 ma, f = 0) outputs disabled cy7c0833v ? ? ? ? 70 100 ? 70 100 ma capacitance part number [29] parameter description test conditions max unit cy7c0831av c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v 13 pf cy7c0832av/cy7c0832bv c out output capacitance 10 pf cy7c0833v c in input capacitance 22 pf c out output capacitance 20 pf notes 26. the voltage on any input or i/o pin can not exceed the power pin during power up. 27. pulse width < 20 ns. 28. i sb1 , i sb2 , i sb3 and i sb4 are not applicable for cy7c0833v because it can not be powered down by using chip enable pins. 29. c out also references c i/o .
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 14 of 31 ac test load and waveforms figure 6. ac test load and waveforms switching characteristics over the operating range parameter description -167 -133 -100 unit cy7c0832av cy7c0831av cy7c0832av cy7c0832bv cy7c0833v min max min max min max f max2 maximum operating frequency ? 167 ? 133 ? 100 mhz t cyc2 clock cycle time 6.0 ? 7.5 ? 10 ? ns t ch2 clock high time 2.7 ? 3.0 ? 4.0 ? ns t cl2 clock low time 2.7 ? 3.0 ? 4.0 ? ns t r [30] clock rise time ?2.0?2.0?3.0ns t f [30] clock fall time ?2.0?2.0?3.0ns t sa address setup time 2.3 ? 2.5 ? 3.0 ? ns t ha address hold time 0.6 ? 0.6 ? 0.6 ? ns t sb byte select setup time 2.3 ? 2.5 ? 3.0 ? ns t hb byte select hold time 0.6 ? 0.6 ? 0.6 ? ns t sc chip enable setup time 2.3 ? 2.5 ? na ? ns t hc chip enable hold time 0.6 ? 0.6 ? na ? ns t sw r/w setup time 2.3?2.5?3.0?ns t hw r/w hold time 0.6?0.6?0.6?ns t sd input data setup time 2.3 ? 2.5 ? 3.0 ? ns t hd input data hold time 0.6?0.6?0.6?ns t sad ads setup time 2.3 ? 2.5 ? na ? ns t had ads hold time 0.6?0.6?na?ns t scn cnten setup time 2.3 ? 2.5 ? na ? ns t hcn cnten hold time 0.6?0.6?na?ns t srst cntrst setup time 2.3 ? 2.5 ? na ? ns r1 = 590 ? r2 = 435 ? c = 5 pf (b) three-state delay (load 2) 90% 10% 3.0 v vss 90% 10% < 2ns < 2ns all input pulses 3.3 v v th = 1.5 v r = 50 ? z 0 = 50 ? (a) normal load (load 1) c = 10 pf output output note 30. except jtag signals (t r and t f < 10 ns [max.]).
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 15 of 31 t hrst cntrst hold time 0.6?0.6?na?ns t scm cnt/msk setup time 2.3 ? 2.5 ? na ? ns t hcm cnt/msk hold time 0.6?0.6?na?ns t oe output enable to data valid ? 4.0 ? 4.4 ? 5.0 ns t olz [31, 32] oe to low z 0?0???ns t ohz [31, 32] oe to high z 04.004.4?5.0ns t cd2 clock to data valid ? 4.0 ? 4.4 ? 5.0 ns t ca2 clock to counter address valid ? 4.0 ? 4.4 ? na ns t cm2 clock to mask register readback valid ?4.0?4.4?nans t dc data output hold after clock high 1.0?1.0?1.0?ns t ckhz [31, 32] clock high to output high z 0 4.0 0 4.4 ? 5.0 ns t cklz [31, 32] clock high to output low z 1.0 4.0 1.0 4.4 1.0 5.0 ns t sint clock to int set time 0.5 6.7 0.5 7.5 0.5 10 ns t rint clock to int reset time 0.5 6.7 0.5 7.5 0.5 10 ns t scint clock to cntint set time 0.5 5.0 0.5 5.7 na na ns t rcint clock to cntint reset time 0.5 5.0 0.5 5.7 na na ns port to port delays t ccs clock to clock skew 5.2 ? 6.0 ? 8.0 ? ns master reset timing t rs master reset pulse width 7.0 ? 7.5 ? 10 ? ns t rs master reset setup time 6.0 ? 6.0 ? 8.5 ? ns t rsr master reset recovery time 6.0 ? 7.5 ? 10 ? ns t rsf master reset to outputs inactive ? 10.0 ? 10.0 ? 10.0 ns t rscntint master reset to counter interrupt flag reset time ?10.0?10.0? nans switching characteristics (continued) over the operating range parameter description -167 -133 -100 unit cy7c0832av cy7c0831av cy7c0832av cy7c0832bv cy7c0833v min max min max min max notes 31. this parameter is guaranteed by design, but is not production tested. 32. test conditions used are load 2.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 16 of 31 jtag timing and switching waveforms parameter description cy7c0831av/cy7c0832av /cy7c0832bv/cy7c0833v unit min max f jtag maximum jtag tap controller frequency ? 10 mhz t tcyc tck clock cycle time 100 ? ns t th tck clock high time 40 ? ns t tl tck clock low time 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t tdih tdi hold after tck clock rise 10 ? ns t tdov tck clock low to tdo valid ? 30 ns t tdox tck clock low to tdo invalid 0 ? ns figure 7. jtag switching waveform test clock test mode select tck tms test data-in tdi te s t d a t a - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 17 of 31 switching waveforms figure 8. master reset figure 9. read cycle [33, 34, 35, 36, 37] mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency be0 ?be1 t sb t hb notes 33. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data is out after the following clk edge and is three-stated after the next clk edge. 34. oe is asynchronously controlled; all other inputs (excluding mrst and jtag) are synchronous to the rising clock edge. 35. ads = cnten = low, and mrst = cntrst = cnt/msk = high. 36. the output is disabled (high-impedance state) by ce = v ih following the next rising edge of the clock. 37. addresses need not be accessed sequentially because ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 18 of 31 figure 10. bank select read [38, 39] figure 11. read-to-write-to-read (oe = low) [40, 41, 42, 43, 44] switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3 notes 38. in this depth-expansion example, b1 represents bank #1 and b2 is bank #2; each bank consis ts of one cypress flex18 device fr om this data sheet. address (b1) = address (b2) . 39. ads = cnten = be0 ? be1 = oe = low; mrst = cntrst = cnt/msk = high. 40. addresses need not be accessed sequentially because ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. 41. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 42. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 43. ce 0 = oe = be 0 ? be 1 = low; ce 1 = r/w = cntrst = mrst = high. 44. ce 0 = be 0 ? be 1 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, because oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three-state the i/o for the write operation on the next ri sing edge of clk.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 19 of 31 figure 12. read-to -write-to-read (oe controlled) [45, 46, 47, 48] figure 13. read with address counter advance [47] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe q n+4 t cd2 t sa t ha t ch2 t cl2 t cyc2 clk address a n counter hold read with counter t sad t had t scn t hcn t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address ads cnten data out notes 45. addresses need not be accessed sequentially because ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. 46. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 47. ce 0 = oe = be 0 ? be 1 = low; ce 1 = r/w = cntrst = mrst = high. 48. ce 0 = be 0 ? be 1 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, because oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three-state the i/o for the write operation on the next ri sing edge of clk.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 20 of 31 figure 14. write with address counter advance [49] figure 15. counter reset [50, 51] switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal data in address t sa t ha cnten ads clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [52] reset address 0 counter write read address 0 address 1 read read address a n address a m read notes 49. ce 0 = be0 ? be1 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, because oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three-state the i/o for the write operation on the next ri sing edge of clk. 50. ce 0 = be0 ? be1 = low; ce 1 = mrst = cnt/msk = high. 51. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. 52. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 21 of 31 figure 16. readback state of address counter or mask register [53, 54, 55, 56] switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n t sa t ha t sad t had t scn t hcn load address external t cd2 internal address a n+1 a n+2 a n t ckhz data out a n* q n+3 q n+1 q n+2 a n+3 a n+4 t cklz t ca2 or t cm2 readback internal counter address increment external a 0 ?a 16 notes 53. ce 0 = oe = be0 ? be 1 = low; ce 1 = r/w = cntrst = mrst = high. 54. address in output mode. host must not be driving address bus after t cklz in next clock cycle. 55. address in input mode. host can drive address bus after t ckhz . 56. an * is the internal value of the address counter (or the mask register depending on the cnt/msk level) being read out on the address lines.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 22 of 31 figure 17. left_port (l_port) wr ite to right_port (r_port) read [57, 58, 59] switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk l r/w l a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 l_port address l_port data in clk r r/w r r_port address r_port data out notes 57. ce 0 = oe = ads = cnten = be 0 ? be 1 = low; ce 1 = cntrst = mrst = cnt/msk = high. 58. this timing is valid when one port is writing, and other port is reading the same location at the same time. if t ccs is violated, indeterminate data is read out. 59. if t ccs < minimum specified value, then r_port is read the mo st recent data (written by l_port) only (2 * t cyc2 + t cd2 ) after the rising edge of r_port's clock. if t ccs > minimum specified value, then r_port is read the most recent data (written by l_port) (t cyc2 + t cd2 ) after the rising edge of r_port's clock.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 23 of 31 figure 18. counter interrupt and retransmit [60, 61, 62, 63, 64, 65] switching waveforms (continued) t ch2 t cl2 t cyc2 clk 3fffd 3ffff internal address last_loaded last_loaded +1 t hcm counter 3fffe cntint t scint t rcint 3fffc cnten ads cnt/msk t scm notes 60. a18x is a nc for cy7c0832av/cy7c0832bv, therefore the interru pt addresses are 3ffff and 3fffe. a18x and a17x are nc for cy7c 0831av, therefore the interrupt addresses are 1ffff and 1fffe. 61. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. 62. ce 0 = oe = be0 ? be1 = low; ce 1 = r/w = cntrst = mrst = high. 63. cntint is always driven. 64. cntint goes low when the unmasked portion of the address counter is incremented to the maximum value. 65. the mask register assumed to have the value of 3ffffh.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 24 of 31 figure 19. mailbox interrupt timing [66, 67, 68, 69, 70] switching waveforms (continued) t ch2 t cl2 t cyc2 clk l t ch2 t cl2 t cyc2 clk r 7ffff t sa t ha a n+3 a n a n+1 a n+2 l_port address a m a m+4 a m+1 7ffff a m+3 r_port address int r t sa t ha t sint t rint notes 66. ce 0 = oe = ads = cnten = low; ce 1 = cntrst = mrst = cnt/msk = high. 67. address ?7ffff? is the mailbox location for r_port of the 9mb device. 68. l_port is configured for write operation, and r_port is configured for read operation. 69. at least one byte enable (be 0 ? be 1 ) is required to be active during interrupt operations. 70. interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of th e read clock.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 25 of 31 table 3. read/write and enable operation (any port) [71, 72, 73, 74, 75] inputs outputs operation oe clk ce 0 ce 1 r/w dq 0 ? dq 17 x h x x high z deselected x x l x high z deselected xlhld in write llhhd out read h x l h x high z outputs disabled notes 71. cy7c0831av has 17 address bits, cy7c0832av/cy7c0832bv has 18 address bits and cy7c0833v has 19 address bits. 72. ?x? = ?don?t care,? ?h? = high, ?l? = low. 73. oe is an asynchronous input signal. 74. when ce changes state, deselection and read happen after one cycle of latency. 75. ce 0 = oe = low; ce 1 = r/w = high.
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 26 of 31 ordering code definitions ordering information cypress offers other versions of this ty pe of product in many different configurat ions and features. the following table contai ns only the list of parts that are currently available. for a comp lete listing of all options, visit the cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices . 512 k 18 (9 m) 3.3 v synchronous cy7c0833v dual-port sram speed (mhz) ordering code package diagram package type operating range 100 cy7c0833v-100bbi 51-85141 144-ball ball grid array (13 13 1.6 mm) with 1 mm pitch industrial 256 k 18 (4 m) 3.3 v synchronous cy7c0832av/cy7c0832bv dual-port sram speed (mhz) ordering code package diagram package type operating range 167 cy7c0832av-167axc 51-85100 120-pin thin quad flat pack (14 14 1.4 mm) (pb-free) commercial 133 CY7C0832BV-133AI 51-85100 120-pin thin quad flat pack (14 14 1.4 mm) industrial cy7c0832av-133axi 120-pin thin quad flat pack (14 14 1.4 mm) (pb-free) 128 k 18 (2 m) 3.3 v synchronous cy7c0831av dual-port sram speed (mhz) ordering code package diagram package type operating range 133 cy7c0831av-133axi 51-85100 120-pin thin quad flat pack (14 14 1.4 mm) (pb-free) industrial temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: xx = bb or a bb = 144-ball bga a = 120-pin tqfp speed grade: xxx = 100 mhz or 167 mhz or 133 mhz xx = v/av/bv = 3.3 v 083x = 0833 or 0832 or 0831 0833 = 512 k 18 (9 m) 0832 = 256 k 18 (4 m) 0831 = 128 k 18 (2 m) technology code: c = cmos marketing code: 7 = dual port sram company id: cy = cypress c cy 083x - xxx x xx x xx 7
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 27 of 31 package diagrams figure 20. 144-ball fbga (13 13 1.6 mm) bb144, 51-85141 figure 21. 120-pin tqfp (14 14 1.4 mm) a120s, 51-85100 51-85141 *d 51-85100 *b
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 28 of 31 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group oe output enable sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microamperes ma milliamperes mm millimeter mv millivolts ns nanoseconds ? ohms % percent pf picofarad vvolts
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 29 of 31 document history page document title: cy7c0831av/cy7c0832av/cy7c0832bv/cy 7c0833v, flex18? 3.3 v 128 k / 256 k / 512 k 18 synchronous dual-port ram document number: 38-06059 rev. ecn no. orig. of change submission date description of change ** 111473 dsg 11/27/01 change from sp ec number: 38-01056 to 38-06059 *a 111942 jfu 12/21/01 updated capacitance values updated switching parameters and i sb3 updated ?read-to-write-to-read (oe controlled)? waveform revised static discharge voltage revised footnote regarding i sb3 *b 113741 kre 04/02/02 updated i sh values updated esd voltage corrected 0853 pins l3 and l12 *c 114704 kre 04/24/02 added discussion of pause/restart for jtag boundary scan *d 115336 kre 07/01/02 revised speed offerings for all densities *e 122307 rbi 12/27/02 power up requirements added to maximum ratings information *f 123636 kre 1/27/03 revise t cd2 , t oe , t ohz , t ckhz , t cklz for the cy7c0853v to 4.7 ns *g 126053 spn 08/11/03 separated out 4m and 9m data sheets updated i sb and i cc values *h 129443 raz 11/03/03 updated i sb and i cc values *i 231993 ydt see ecn removed ?a particular port can write to a certain location while another port is reading that location.? from functional description. *j 231813 wwz see ecn removed 36 devices (c y7c0852/cy7c0851) from this datasheet. added 0.5 m, 1 m and 9 m 18 devices to it. changed title to flex18 3.3 v 32 k/64 k/128 k/256 k/512 k 18 synchronous dual-port ram. changed datasheet to accommodate the removals and additions. removed general jtag description. updated jtag id codes for all devices. added 144-ball fbga package for all devices. updated selection guide table and moved to the front page. updated block diagram to reflect 18 configuration. added preliminary status back due to the addition of the new devices. *k 311054 ryq see ecn minor change: correct the revision indicated on the footer. *l 329111 spn see ecn updated marketing part numbers updated trsf *m 330561 ruy see ecn added byte select operation table *n 375198 ydt see ecn removed preliminary status added i sb5 changed t rscntint to 10ns *o 391525 spn see ecn updated counter reset section to reflect what is loaded into the mirror register *p 414109 lij see ecn corrected ordering codes for 0831 devices in the 133 mhz speed bin. added cy7c0833av-133bbi. *q 461113 ydt see ecn changed vddio to vdd (typo) added lead(pb)-free parts corrected typo in dc table *r 2544945 vkn/aesa 07/29/08 updated template. updated ordering information *s 2668478 vkn/pyrs 02/04/09 added cy7c0832bv part added footnote #1 updated ordering information table
cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v document #: 38-06059 rev. *w page 30 of 31 *t 2897087 rame 03/22/10 removed obsolete parts from ordering information table updated package diagrams *u 3051710 admu 10/07/2010 removed inactive part cy7c 0831av-133bbxi from ordering information table. removed mention of previously removed parts added ordering code definition added toc *v 3351984 admu 08/23/2011 updated features . updated product selection guide . updated pin configurations . updated boundary scan hierarchy for 9-mbit device . updated switching characteristics . added acronyms and units of measure . updated in new template. *w 3403638 admu 10/13/2011 removed pruned part cy7c0832av-133axc from ordering information updated package diagrams . document history page (continued) document title: cy7c0831av/cy7c0832av/cy7c0832bv/cy 7c0833v, flex18? 3.3 v 128 k / 256 k / 512 k 18 synchronous dual-port ram document number: 38-06059 rev. ecn no. orig. of change submission date description of change
document #: 38-06059 rev. *w revised october 13, 2011 page 31 of 31 flex18 is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be th e trademarks of their respective holders. cy7c0831av, cy7c0832av cy7c0832bv, cy7c0833v ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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